Silicon wafer support fixture with roughended surface

ABSTRACT

A silicon-based wafer support tower particularly useful for batch-mode thermal chemical vapor deposition. The surfaces of the silicon tower are bead blasted to introduce sub-surface damage, which produces pits and cracks in the surface, which anchor subsequently deposited layer of, for example, silicon nitride, thereby inhibiting peeling of the nitride film. The surface roughness may be in the range of 0.25 to 2.5 μm. Wafer support portions of the tower are preferably composed of virgin polysilicon. The invention can be applied to other silicon parts in a deposition or other substrate processing reactor, such as tubular sleeves and reactor walls. Tubular silicon members are advantageously formed by extrusion from a silicon melt.

RELATED APPLICATION

This application is a division of Ser. No. 09/860,392, filed May 18,2001 and to be issued on Sep. 19, 2006 as U.S. Pat. No. 7,108,746,incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention relates generally to semiconductor processing. Inparticular, the invention relates to wafer support fixtures used inbatch-mode chemical vapor deposition.

2. Background Art

The fabrication of silicon integrated circuits typically involves one ormore steps of chemical vapor deposition (CVD). Many advanced depositionprocesses use plasma enchanced CVD to activate the chemical reactionresulting in the deposition of the film from a precursor gas. The plasmaprocess allows low temperature deposition. On the other hand, thermalCVD is performed at elevated temperatures to thermally activate thechemical reaction resulting in the deposition of the film from aprecursor gas. The temperatures associated with thermal CVD tend to bemuch higher than those for plasma enhanced CVD, but thermal CVDtemperatures fall within a wide range depending upon the material beingdeposited and the precursor gas.

Thermal CVD is typically utilized for the deposition of silicon nitrideand polysilicon. The silicon nitride is used, for example, for etch stoplayers and anti-reflective coatings. Silicon nitride has a nominalcomposition of Si₃N₄, but some compositional variation is expected, suchas SiN_(x), where x ranges between 1.0 and 1.5. Polysilicon ispolycrystalline silicon. It is used for anti-reflective coating and,when doped, for interconnects and electrodes.

Despite the trend to single-wafer processing chambers, batch processingfor thermal CVD continues to be widely practiced because of its highthroughput and the relatively low cost of equipment. Furthermore,thermal CVD can produce highly uniform films in batch processing. Inbatch CVD processing, a large number of silicon wafers are loaded onto asupport fixture that is placed into a thermal CVD reactor. Typically,the support fixture is a tower in which the multiple wafers aresupported horizontally and spaced vertically apart. Some applicationscontinue to use boats as support fixture in which the multiple wafersare supported substantially vertically and spaced horizontally apart.

In the case of the deposition of silicon nitride, the precursor gas istypically composed of silane or a chlorosilane and a nitrogen sourcesuch ammonia. At elevated temperatures, typically in the range of 600 to800° C. but sometimes extending down to 400° C. or even lower, theprecursors react near the surface of the wafer to deposit siliconnitride on the wafer surface. In the case of chlorosilane and ammoniaprecursors, the reaction products are Si₃N₄ and NH₄Cl. The formerdeposits on the wafer while the latter is volatile and is evacuated fromthe furnace. However, thermal CVD tends to coat all surfaces exposed inthe furnace. In particular, the support tower is typically coated withas much silicon nitride as is the wafer.

Quartz has in the past been the most prevalently used material forsupport towers used in a thermal CVD process. Quartz has a chemicalcomposition of amorphous silicon dioxide, which is compatible with mostsilicon processing. At the relatively low temperatures usuallyexperienced in CVD, whether thermal or plasma enhanced, quartz remainsin a glassy state with a very smooth surface so that it is a very cleanmaterial. However, as the feature sizes on integrated circuits hasdecreased to 0.18 μm and even smaller, quartz support towers havenonetheless experienced substantial problems with producing particles.These particulates fall on the wafer and can significantly reduce theyield of operable integrated circuit dies obtained from the wafer.

Often integrated circuit fabrication is monitored by measuring thenumber of particles added to a wafer by any step of the fabricationprocess. It has been found in thermal CVD of silicon nitride that thenumber of particles generally increases with the number of runs orbatches that the quartz tower has processed. As illustrated in FIG. 1, anew tower produces relatively few particles. Thereafter, the number ofparticles increases with the number of runs, but up to about forty runsthe number is acceptable, though still somewhat high. However, aftersome number of runs, the number of particles greatly increases to atotally unacceptable level. It is believed that the origin of theproblem is that the silicon nitride is also depositing on the quartztower. For 40 runs of depositing 0.15 μm of silicon nitride, a typicalnitride layer thickness in an integrated circuit, the nitride build upon the tower may be 6 μm. Silicon nitride has a coefficient of thermalexpansion that is significantly different than that of quartz, about3×10⁻⁶ versus 0.5×10⁻⁶/° C., and the nitride does not bond well with theglassy quartz surface. Differential thermal expansion between the twomaterials as the tower is cycled between room temperature and therelatively modest thermal CVD temperatures causes the thickly depositednitride to peel from the quartz and to produce nitride particles, someof which settle on the wafers.

For these reasons, it is typical practice in a production environment touse a tower only for a number of runs somewhat below the experimentallydetermined point at which the particle count rapidly increases, forexample, thirty runs for the data displayed in FIG. 1. It is commonpractice to then clean the quartz tower in bath of hydrofluoric acid andnitric acid to remove the silicon nitride and to return the cleanedtower to service for another cycle of runs. However, the baselineparticle count for a cleaned tower is somewhat higher than that for anew tower, and the number of runs before onset of unacceptable particlecount is reduced by about 25%. As a result, quartz towers are typicallydiscarded after only two or three cycles. Although quartz towers arerelatively inexpensive, such short life greatly increases the cost ofownership (COO) when measured per wafer. Also, the necessity of changingout towers and cleaning towers complicates the work flow and reducesproductivity.

Furthermore, the baseline particle counts for quartz towers are stillhigh, and the onset of greatly increased counts is somewhat variable.Both factors reduce the yield of operable dice obtained from the wafers.

Some of these reasons have prompted the use of silicon carbide towers.Bulk silicon carbide is typically formed by a sintering process, whichproduces a material containing a high fraction of impurities. For thisreason, the sintered material is usually covered with a layer of CVDsilicon carbide. As long as the CVD layer is not punctured,contamination is not a problem. The peeling problem is not totallyeliminated, but if, after a nitride buildup of about 20 μm on thesilicon carbide tower, it is cleaned in aqua regia (HF/HNO₃) for up to aweek, the tower can be used almost indefinitely. However, the CVDsilicon carbide film is fragile, and a single pin hole through the filmruins the coating protect so the tower must be scrapped. Entire towersof CVD silicon carbide can be made, but they are very expensive.

Accordingly, it is greatly desired to provide a support tower that isnot subject to such particle problems and can be used for many more runswithout cleaning or replacement.

SUMMARY OF THE INVENTION

The invention includes a method of chemical vapor deposition (CVD),particularly thermal CVD, and more particularly deposition of siliconnitride, polysilicon, and related materials, onto multiple waferssupported on a silicon fixture, for example, a tower. Preferably, thesilicon fixture is composed of virgin polysilicon. Also, preferably,surfaces of the silicon tower are subjected to surface treatment, suchas bead blasting by hard particles, for example, of silicon carbide. Thesurface treatment may be characterized as introducing sub-surface damagein the silicon part.

The invention also includes such a silicon fixture and its fabricationmethod. The surface of the fixture has a roughness preferably in therange of 10-100 microinches Ra (0.25-2.5 μm), more preferably 20-75microinches Ra (0.5-1.9 μm), and most preferably 35-50 microinches Ra(0.9-1.25 μm).

The invention further includes other surface treated silicon partsusable in a CVD reactor or other high-temperature substrate processingreactor.

Silicon tubular members may advantageously be used for liners in CVDreactors and for tubular reactor walls used in high-temperatureprocessing. Such silicon tubular members are conveniently formed byextrusion, whether or not the tube is surface treated.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic chart showing the generation of particles duringbatch thermal chemical vapor deposition using a quartz tower of theprior art.

FIG. 2 is an orthographic view of a silicon tower fabricated accordingto the invention and usable in the processes of the invention.

FIG. 3 is a cross-sectional view of a surface of the silicon tower afterbead blasting.

FIG. 4 is a cross-sectional view of the silicon tower surface of FIG. 3after deposition of a pre-coat layer.

FIG. 5 is a cross-sectional view of the silicon tower surface of FIG. 4after many runs of depositing silicon nitride.

FIG. 6 is a schematic cross-sectional view of a thermal CVD reactor inwhich a process of the invention may be practiced and in which the toweror shield of the invention may be used.

FIG. 7 is a schematic orthographic view of a tubular reactor havingsilicon sidewalls.

BRIEF DESCRIPTION OF THE PREFERRED EMBODIMENTS

Silicon fixtures, particularly horizontally extending boats, have beenfrequently suggested and occasionally used in the past. However, theirassembly has presented sufficient problems to prevent the widespread useof silicon towers. Many of these problems with silicon support fixtureshave been addressed in a set of patents, U.S. Pat. Nos. 6,196,211,6,205,993, and 6,225,594 to various of Zehavi, Davis, and Delaney. Boyleet al. in U.S. patent application, Ser. No. 09/608,291, filed Jun. 30,2000, now issued as U.S. Pat. No. 6,455,395, and incorporated herein byreference in its entirety, disclose in detail a method of fabricatingone embodiment of such a silicon tower 10, illustrated in FIG. 2. Thetower 10 includes multiple silicon legs 12 joined at opposed ends tosilicon bases 14. Teeth 16 are cut into the legs 12 to support thewafers.

It is preferred that at least the legs 12 are composed of virginpolysilicon (virgin poly) formed from the chemical vapor deposition ofsilane or chlorosilane. Such a material is virtually free ofcontaminants, particularly the rapidly diffusing metals so deleteriousto silicon integrated circuits. The bases may be formed of Czochralski(CZ) silicon, preferably polysilicon although monocrystalline may beused, since virgin poly is not typically available in such largediameters. Other forms of silicon such as cast silicon may be used. Theprocess includes joining the legs 12 to the bases 14 with a spin-onglass (SOG) or other glass-like compound followed by high-temperatureambient annealing at preferably between 1025 and 1400° C. to vitrify theSOG and bond it to the already oxidized silicon parts. After assembly,the tower 10, including both the legs 12 and bases 14, is subjected to asurface treatment to introduce controlled sub-surface damage in thesilicon.

Such a surface treatment virtually eliminates the particle problemusually associated with thermal CVD of silicon nitride. We believe thatthe surface treatment not only removes the thick oxide layer formed inthe SOG anneal, but also, as illustrated in the cross-sectional view ofFIG. 2 produces pits 20 and cracks 22 penetrating into the treatedsurface 24 of the silicon part 26 of the tower 10. The silicon part 26may be one of the legs 12 or one of the bases 14.

When the tower enters service, it is preferably first subjected to apre-treatment similar to a typical nitride CVD deposition in which asilicon nitride pre-coat layer 28 not only covers the part surface 24but also fills the pits 20 and cracks 22 to produce a smooth pre-coatsurface 30. Preferably, during the pre-treatment, no wafers are insertedin the slots to be used in production. The silicon nitride in the pits20 and cracks 22 firmly anchors the pre-coat layer 28 to the siliconpart. Thereafter, when the tower enters normal production, subsequentlydeposited silicon nitride layers 32 are sequentially deposited over thesilicon nitride pre-coat layer 28, which is firmly anchored to thesilicon part 26. Although differential thermal expansion continues toexist between the nitride layers 32 and the underlying bulk silicon 26,the force exerted at the interface is insufficient to peel the nitridelayers 32 from the part 26.

An effective method of work treating the silicon surface is to roughenit by bead blasting, which is similar to industrial sand blasting. Apreferred such method is to blast the surface with particles of siliconcarbide of 220 grey grit in a Model 48/PP dry blaster available fromTrinity Tool Co. of Fraser, Mich. Particle velocity is controlled by anexit pressure of between about 20 and 80 psi. In the bead blasting, theblasting wand is manually swept over all exposed surfaces of theassembled tower. The blasting need not visibly roughen the siliconsurface. The silicon surface following the preceding high-temperatureSOG anneal has a bluish color, arising from the thick surface oxidation.The blasting is continued until the bluish color turns gray, indicativeof silicon with perhaps a very thin native oxide. Preferably, thesilicon carbide particles are relatively pure to above 99%, particularlywith respect to metals. Use of particles with significant metalcontaminants will likely introduce the metal into the silicon part,rendering the treated part much less useful for processing siliconintegrated circuits.

Following bead blasting, the treated silicon surface is cleaned byvigorously washing it with a biodegradable, non-phosphate detergent suchas Escolex to remove silicon particles clinging to the surface. A finalclean with a high-pressure carbon dioxide gun, such as Sno Blo, removesany remaining particles. The final surface roughness has been measuredto be typically about 32 microinches (0.8 μm) on the virgin poly legsand 50 microinch (1.3 μm) on the CZ bases. A preferred range of surfaceroughness, particularly for the legs, is 10 to 100 microinches Ra (0.25to 2.5 μm Ra) A more preferred range is 20-75 microinches Ra (0.5-1.9 μmRa), and a most preferred range is 30-50 microinches Ra (0.75-1.25 μmRa).

It is preferred that no post-treatment etching be performed as thiswould likely remove the pits and cracks. Post-treatment polishing isalso not preferred, except possibly in the wafer bearing surfaces which,in a preferred embodiment, are cut into teeth slanting upwards from thelegs at 1 to 3° from the horizontal.

Other hard particles may be used for the blasting, such as ceramics.However, the material must be substantially free of metals known toreadily diffuse in silicon and affect its semiconductor qualities. Othertypes of surface treatment are possible, such as lapping and grinding.However, these processes are dirty, and offer no apparent advantage.

The silicon tower 10 fabricated according to the above process is usedin a batch CVD reactor 40, as illustrated in FIG. 6, which is heated bya resistive coil 42. The reactor is supplied with precursor gasesincluding silane or a chlorosilane such as SiClH₃ and ammonia (NH₃) fromsource 44, 46, and a vacuum (exhaust) pump 48 evacuates reactants fromthe interior of the reactor 40. The pump 48 may maintain the interior ofthe reactor 40 at anywhere in the range from approximately atmosphericpressure for atmospheric pressure CVD (APCDV) down to about 10 Torr forlow pressure CVD (LPCVD). Multiple wafers 50 are loaded into the tower10 and processed as described above to deposit the silicon nitride inone batch run. When a boat instead of a tower is used, the thermal CVDreactor is typically in the form of a horizontally extending tube, intowhich the boat bearing multiple wafers is horizontally inserted.

Such surface-treated silicon towers can be used for hundreds tothousands of runs. The nitride build up seems to be limited only by theaccumulating nitride filling the slots between the teeth and impedingmechanical clearance of the wafers. Such thicknesses of silicon nitridecan be removed by reslotting the teeth or by a long etch in hothydrofluoric acid.

Polysilicon is also frequently deposited by thermal CVD typically usinga silane or chlorosilane precursor gas. A silicon tower for polysiliconCVD deposition is advantageous since the CVD polysilicon is well matchedto the virgin poly and possibly other forms of silicon in the tower. Asmooth silicon tower surface may suffice for polysilicon deposition.However, it has been observed that CVD polysilicon flakes from ICwafers. Accordingly, the surface treatment of the invention is useful inproviding additional bonding between the bulk silicon parts and thedeposited polysilicon layers. The silicon tower may be pre-coated withthe same material as that deposited in batch CVD processing of thewafers. That is, for batch deposition of silicon nitride, the precoatingmay form a silicon nitride layer while, for batch deposition ofpolysilicon, the precoating may form a polysilicon layer.

Although the invention is particularly useful for support towers andboats supporting multiple wafers, it may also be applied to other partsthat are exposed to deposition. For example, a sleeve 52 may be insertedin the CVD reactor 40 of FIG. 6 to control the flow of gases in thereactor. Whatever deposition occurs also coats the interior of thesleeve 52, which may be removed and replaced. In the past, the sleeve 52has been composed of quartz. A quartz sleeve suffers many of the sameproblems as a quartz tower. Instead, according to the invention, thesleeve 52 is composed of silicon having a tubularly shaped wall of about2 to 5 mm thickness. At least its interior walls are surface treated bybead blasting or the like to provide a good anchor for the deposition ofmany layers of silicon nitride. The lifetime of the treated siliconsleeve 52 is substantially longer than that of a quartz sleeve.

A similarly shaped silicon chamber part is a silicon reactor tube 60illustrated in the schematic orthographic view of FIG. 7. It has acircularly symmetric wall 62 of thickness t enclosing a bore 64 ofdiameter D. A resistive heater 66 is wrapped around the tube 60 and ispowered by a power supply 68 to heat the interior of the reactor toelevated temperatures. Other forms of heating are possible, such asradiant or RF inductive heating. If the silicon tube 60 has sufficientlyhigh doping so as to be highly conductive, the RF energy may be coupleddirectly into the tube 60, in which case the power supply 68 supplies RFpower rather than AC or DC and the wire 66 may be offset from the tubewall 62.

The diameter D is large enough to accommodate a wafer tower or waferboat supporting a number of wafers. That is, the diameter D is somewhatlarger than the wafer diameter of, for example, 200 or 300 mm. For atower, the tube is arranged vertically; for a boat, the tube is arrangedhorizontally and preferably the boat is support on rails cantileveredparallel to the tube wall 62. In either case, the support fixture loadedwith wafers is placed in the reactor tube. In a vertically arrangedreactor, either the tube is lowered over a stationary tower or the towermay be inserted vertically into a stationary tube. On the other hand, awafer boat is moved horizontally into a stationary horizontally arrangedreactor tube.

The silicon tube 60 is held between unillustrated end caps, preferablyformed of surface-treated silicon, providing a support for the tower orboat and ports for the supply gases and exhaust or vacuum pump of FIG.6. If necessary, the end caps are vacuum sealed to the tube 60 for therelatively modest vacuums required. The thickness of the tube wall 62 ispreferably at least 3 mm and more preferably at least 5 mm. Such areactor tube thereby allows a large portion of the exposed surfaces ofthe reactor to be composed of high-purity silicon. Such reactor tubes,previously made of quartz or sometimes silicon carbide, are used forthermal CVD of silicon nitride and polysilicon, as previously described,for wet or dry thermal oxidation of silicon, for diffusion doping froman ambient including the doping material, inert annealing including adopant drive-in, and for other high temperature processes.Advantageously, especially for thermal CVD, the interior surface of thetube wall 64 is surface treated to provide additional adhesion to thedeposition material.

Other parts in this or other deposition chambers, such as pedestals,pedestal rings, and rails, typically formed of quartz in the past, mayinstead be formed of silicon, preferably virgin poly if it is availablein adequate sizes, and thereafter surface treated as described above.

Although virgin poly is particularly advantageous for silicon partswhich contact the wafer, other chamber parts such as the above describedsleeve and wall do not require the very high purity levels associatedwith virgin poly. The surface treatment described above may be appliedto other forms of silicon, for example, float zone (FZ) silicon, CZsilicon, cast silicon, edge film grown (EFG) silicon, the last two ofwhich are prevalently used for solar cells, or other types such asextruded silicon. It is also possible, to perform the described surfacetreatment on a silicon film deposited on another base material, forexample, by CVD.

At the present time, virgin polysilicon is not available in diameters ofgreater than 200 mm required for the sleeve and reactor tube describedabove. Silicon of lesser purity is acceptable in many processingapplications in which a high-temperature silicon part does not touch thesilicon wafer. Nonetheless, the silicon parts should be made of siliconthat is substantially pure, for example, has a impurity atomic fractionof metals of less than one part per million and of other componentsincluding oxygen, nitrogen, and carbon of substantially less than 1% andpreferably less than 50 parts per million. Alternatively, the siliconmay be characterized as being semiconductive.

One method of forming the tubular sleeve and wall described above isextrusion of silicon in a tubular shape in a process also called edgefilm growth (EFG). Some older technology for doctor-blade extrusion ofsilicon is disclosed by Grabmaier et al. in U.S. Pat. Nos. 4,330,358 and4,357,201. This technology sinters the extruded form and uses germaniumsintering aids, including semiconductor dopants if desired. More recenttechnology including extruding silicon tubes is disclosed by Stormont etal. in U.S. Pat. No. 4,440,728 and by Harvey et al. in U.S. Pat. No.5,102,494. GT Equipment Technologies, Inc. of Nashua, N.H. hascommercialized and markets technology for extruding large hollow siliconmembers and sells an extruder under the tradename GIi EFG Puller. It haslong been known to form small-diameter sapphire tubes by EFG.

Ten-sided silicon chamber walls may be formed by bonding together tensilicon plates in a closed pattern as one would assemble staves into abarrel. However, this technique is not always successful because thepolygonal shape introduces non-uniform flow patterns and the bondingagent used to bond the plates together is a contaminant forsemiconductor processing.

The silicon parts of the invention are not limited to batch mode thermalCVD reactors. They can be used for plasma CVD and other low temperatureprocesses performed with wafer temperatures below 400° C. For example, asingle-wafer plasma CVD reactor has a side wall and a dome onto whichthe intended deposition material is likely to also be deposited. In thepast, the wall and dome have been typically made of quartz, and a plasmacleaning process has been used to clean the wall and dome surfaces,either between every wafer run or on a less frequent schedule. If thequartz wall, dome, or other part is replaced with a correspondingsilicon part surface treated as described above, the plasma cleaning maybe eliminated or perhaps delayed until a planned maintenance shutdown.Plasma etching reactors are also subject to deposition of polymericmaterial and other residues on the chamber walls and parts. Theroughened silicon described above will more firmly anchor the residuesand reduce the production of particulates.

The invention thus provides a generic approach for reducing particles insubstrate processing reactors by the use of surface worked siliconparts. Nonetheless, the silicon material of the parts is readilyavailable at reasonable costs and does not require complex processing.

1. A silicon support fixture, comprising a plurality of silicon partsfixed together, configured to support a plurality of wafers, and havingat least major surface portions with a roughened surface havingsub-surface damage including pits and cracks penetrating the roughenedsurface.
 2. The fixture of claim 1, wherein the roughened surface has aroughness in a range between 0.25 and 2.5 μm Ra.
 3. The fixture of claim2, wherein said range extends between 0.5 and 1.9 μm Ra.
 4. The fixtureof claim 3, wherein said range extends between 0.75 and 1.25μm Ra. 5.The fixture of claim 1, wherein at least some of said silicon parts arecomposed of virgin polysilicon.
 6. The fixture of claim 1, furthercomprising silicon nitride filled into the pits and cracks.
 7. A siliconwafer processing reactor for treating a silicon wafer, including: aprocessing chamber for a silicon wafer supported therein; and a partexposed in said chamber composed of silicon and having a roughenedexposed surface including pits and cracks penetrating the roughenedexposed surface.
 8. The reactor of claim 7, wherein said part is asupport supporting a plurality of said wafers.
 9. The reactor of claim7, wherein the roughened exposed surface has a surface roughness in arange between 0.25 and 2.5 μm Ra.
 10. The reactor of claim 9, whereinsaid range extends between 0.5 and 1.9 μm Ra.
 11. The reactor of claim10, wherein said range extends between 0.75 and 1.25 μm Ra.
 12. Thereactor of claim 7, wherein at least some of said silicon parts arecomposed of virgin polysilicon.
 13. The reactor of claim 7, furthercomprising silicon nitride filled into the pits and cracks.